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The backend access block allows a processor connected to the core backend to access the DMA registers and initiate a
DMA transfer.
Datapath
The datapath block provides the data control and storage path between the backend and the PCI bus. It contains four
sub-blocks: the PCI datapath, the PCI datapath controller, the backend and FIFO controller, and the internal data
storage memory.
The PCI datapath controller is responsible for controlling the PCI control signals and coordinating the data transfers
with the backend controller for both Target and Master operations.
The PCI datapath block selects which data should be routed to the PCI bus. Data may come from the PCI
configuration block, the DMA register block, or the internal data storage. The datapath block also generates and verifies
the PCI parity signals.
The backend controller implements the FIFO control logic. This interfaces to the user’s backend logic and moves data
from the backend interface into the internal storage. It also includes logic that monitors how much data is actually
transferred on the PCI bus. The backend controller can recover data that has not actually been transferred, such as when
a Master transfer is terminated with a disconnect without data.
Internal Data Storage
CorePCIF includes a 64-word internal memory block that is used to store data being moved from the backend to the
PCI bus. Data being transferred from the PCI bus to the backend is not stored internally in the core.
This data storage performs two functions. First, it implements a four-word FIFO that decouples the PCI data transfers
from the backend data transfers, thereby increasing throughput. Second, it provides storage for the FIFO recovery logic
used to prevent data loss when the backend is connected to a standard FIFO.
Each of the seven supported BARs (six BARs and the Expansion ROM) is allocated eight words of memory. BAR 0 is
allocated locations 0–7, BAR 1 is allocated 8–15, etc. The Expansion ROM is allocated locations 48–55, and the
remaining eight locations are not used. Each word is 32 bits wide for 32-bit implementations and 64 bits wide for 64-bit
implementations.
For the Axcelerator, ProASIC PLUS , ProASIC3, and ProASIC3E families, the data storage is implemented using FPGA
memory resources. For SX-A and RTSX-S families, the storage is implemented using FPGA logic resources. For the
RTAX-S family, the storage can be implemented using FPGA logic resources or memory resources. Each BAR will
require at least 256 logic modules to implement the storage. Storage is only required for the enabled BARs.
When the SLOW_READ parameter is set, the internal data storage is not implemented, eliminating the need for
FPGA memory resources. Instead, the data throughput rate is reduced to prevent data loss.
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相关PDF资料
COREU1LL-AR
IP MODULE COREU1LL
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CORR-8BIT-XM-UT2
SITE LICENSE IP CORRELATOR XP
CP2-GSA-L
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CP2-HSA110-1
CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4
CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F
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相关代理商/技术参数
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制造商:Philips Lumileds 功能描述:
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